1. Technical Field
The present invention relates in general to integrated circuit manufacturing and, in particular, to a method and system for improving yield loss caused by wafer manufacturing line variations. Still more particularly, the present invention is related to a method and system for providing quality control on wafers running on a wafer manufacturing line without requiring process changes or product redesign.
2. Description of Related Art
A typical manufacturing process for an integrated circuit begins with the fabrication of a semiconductor wafer containing hundreds or even thousands of identical chip that each includes integrated circuits. Following wafer fabrication, a quick first pass wafer probe is typically performed in an attempt to identify chips on the wafer having defects. Depending on the number and type of defects that are detected, corrective action, such as laser fusing, may be taken to improve yield. Once any such corrective steps have been performed, the wafer may be subjected to a second pass wafer probe to determine the efficacy of the corrective steps in addressing detected defects, and any chips failing the second pass wafer probe are marked as faulty.
Following the second pass wafer probe, the wafer is scribed into chips, and chips passing the wafer probes are packaged into packaged integrated circuit devices. After packaging, the packaged integrated circuit devices are then subjected to device-level testing to detect additional faults. Such device-level testing may include a burn-in test in which the packaged integrated circuit devices are subjected to high ambient temperatures and tests of long duration in order to discover early life failures. In addition, the device-level testing may include scan based testings, functional logic testings and DC and AC characteristic testings.
The central focus in the conventional manufacturing process outlined above is to improve yield and decrease the number of integrated circuits, devices and modules that are discarded due to uncorrected faults. Accordingly, much effort has been focused on the detection and correction of faults during the manufacturing process. Unfortunately, test identifies yield issues after the manufacturing process has been implemented and the product already designed. Changes to either the manufacturing process or the product design are very expensive and time-consuming.
Since manufacturing processes that control resistance are impacted by the need to adjust base process elements such as threshold voltage, resistances often are not centered at the middle of line specifications and expensive process changes such as adding additional masking levels or complete product design are needed to ensure that the product will meet acceptable yield levels. Current techniques to modify resistance through the use of fuses requires installation of custom test circuits within the chip, which requires the use of substantial silicon area and long expensive test times. Such technique is seldom used because of the associated high expense.